Jafari, F and Lu, Z and Jantsch, A (2015) Least Upper Delay Bound for VBR Flows in Networks-on- Chip with Virtual Channels. ACM Transactions on Design Automation of Electronic Systems (TODAES), 20 (35). ISSN 1084-4309
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Abstract
Real-time applications such as multimedia and gaming require stringent performance guarantees, usually enforced by a tight upper bound on the maximum end-to-end delay. For FIFO multiplexed on-chip packet switched networks we consider worst-case delay bounds for Variable Bit-Rate (VBR) flows with aggregate scheduling, which schedules multiple flows as an aggregate flow. VBR Flows are characterized by a maximum transfer size, peak rate, burstiness, and average sustainable rate. Based on network calculus, we present and prove theorems to derive per-flow end-to-end Equivalent Service Curves (ESC) which are in turn used for computing Least Upper Delay Bounds (LUDBs) of individual flows. In a realistic case study we find that the end-to-end delay bound is up to 46.9% more accurate than the case without considering the traffic peak behavior. Likewise, results also show similar improvements for synthetic traffic patterns. The proposed methodology is implemented in C++ and has low run-time complexity, enabling quick evaluation for large and complex SoCs.
| Item Type: | Article |
|---|---|
| Keywords: | Network-on-chip (NoC), performance evaluation, network calculus, worst-case delay bound, FIFO multiplexing |
| Faculty / Department: | Faculty of Human and Digital Sciences > Mathematics and Computer Science |
| Depositing User: | Matt Butler |
| Date Deposited: | 05 Feb 2016 11:36 |
| Last Modified: | 05 Feb 2016 11:36 |
| URI: | https://hira.hope.ac.uk/id/eprint/652 |
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